Job Description

Cupertino, California, United States Hardware

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for all aspects of physical design verifications including: physical verification methodology for SOC, full chip integration flows, physical verification convergence, and closure, and final signoff. Apply knowledge of detailed block level analysis, work on chip floor planning and block interface issues, and understand deep submicron process technology. Work with process variation, various timing margins and derates, and detailed tool /runset settings. Work with both Physical Design Engineers and foundry for new PDK evaluation and qualification, block level physical verification debugging, full chip level debug and rule settings, and work on detailed specifications for block, block assemble level, and full chip level validation specs. Execute physical verification runs, maintain and innovate scripts and infrastructure, and provide documentation for guidelines and specs. Apply strong signoff ownership to ensure first silicon success. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 - $264,200/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Bachelor’s degree or foreign equivalent in Electrical Engineering or related field, and 5 years of progressive, post baccalaureate experience in the job offered or related occupation.
• 5 years of experience with each of the following skills is required:
• Utilizing very-large-scale integration (VLSI) design and experience understanding logic design, data path analysis and digital design flow.
• Experience in floor planning, placement and optimization, physical design routing and physical verification, using PnR and PDV (Calibre) CAD tools.
• Experience performing automation, writing scripts and implementing design, using tool command language (TCL) and shell scripting.
• Experience in Power, Performance and Area analysis
• Analyzing Static timing and Static & Dynamic voltage
• Experience in Physical verification, and experience in layout versus schematic checks.
• Understanding of device physics, semiconductor process and interconnect electrical behaviors, including experience identifying solutions with signoff check violations.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Add to Favorites Physical Design Engineer

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