Job Description

This range is provided by Socionext US. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$170,000.00/yr - $210,000.00/yr

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Physical Design Engineer – Milpitas, CA

Description

Socionext Inc. (SNI) is an innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage and other dynamic technologies that drive today’s leading-edge applications. Socionext combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, Socionext Inc. is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Socionext America Inc. (SNA), a wholly owned subsidiary of SNI.

We are seeking a Physical Design Engineer . This is a hands-on technical position and will have opportunities to work on a variety of challenging designs. Critical to this position is the ability to articulate technical discussions with ASIC Customers and design teams and work closely with customer, frontend and integration teams to ensure successful tape outs.

Primary Responsibilities:

• Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
• Chip/Block Level Floorplanning and pin assignment
• Review top-level/block-level clock specifications for completeness and feasibility
• Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
• Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
• Presentations and Customer Interaction in customer meetings

Necessary Qualifications:

BSEE, with 7+ years of experience or equivalent experience. MSEE preferred.

Experience in ASIC Physical Design; Experience in an SoC product development organization with tape outs at 28nm/16nm design nodes and lower.

Hands-on Experience with implementation EDA tools like ICC2/Innovus.

Scripting (Perl/Tcl/Python) is required.

Good understanding of ASIC frontend design.

Experience in both Flat and Hierarchical layouts.

Strong problem-solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.

Experience with power analysis and IR-drop tools (prime power/Redhawk) and Static Timing Analysis (Primetime).

Experience with Physical Verification and fix PV errors in layout.

Expert handling of Verilog HDL based Netlists, Physical design libraries.

Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design, Engineering, and Manufacturing

• Industries

  Semiconductor Manufacturing

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Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

Disability insurance

Tuition assistance

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